1.Technical Field
The invention disclosed broadly relates to semiconductor logic circuits and more particularly relates to an improved register file circuit.
2. Background Art
In modern complex logic function design, such as in the design of microprocessors, a plurality of registers need to be rapidly accessed, each register being able to store a byte or word of data. These registers must be accessed at speeds which are no slower than the logic speeds of other combinatorial logic circuits in the complex logic function. Typical applications such as microprocessors require as many as 16 fast access registers for storing operands, addresses, status words, etc. It is desirable to design the plurality of registers in a contiguous block to enhance both density and performance characteristics. Such a contiguous block of registers is referred to generally as a register file. A typical application of a register file is in the prefetching and storage of a plurality of instructions which are then sequentially read out from consecutive ones of the registers in the register file.
In order to test the circuits in complex logic functions on an integrated circuit chip, the technique of level sensitive scan design (LSSD) is required. In its most elementary form, level sensitive scan design principles involve the use of a dedicated serial data path from an input pad to the serial inputs of concatenated LSSD shift registers for the purpose of scanning in test data which is then output during a testing interval to embedded logic on the integrated circuit chip to be tested. During the testing interval, the embedded logic processes the test data input from the LSSD scan string and outputs the result of that logical processing to an output LSSD shift register associated with the embedded logic. That output LSSD shift register then serially outputs the test result data to the same or to another LSSD scan string, which result data is serially output from the chip for test result analysis These principles are described in greater detail in the following related patents:
U.S. Pat. No. ,761,695 entitled "Method of Level Sensitive Testing a Functional Logic System," to Edward B. Eichelberger and of common assignee; U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System," to Edward B. Eichelberger and of common assignee; U.S. Pat. No. 3,806,891 entitled "Logic Circuit for Scan-In/Scan-Out," to Edward B. Eichelberger, et al. and of common assignee; and U.S. Pat. No. 4,071,902 entitled "Reduced Overhead for Clock Testing in a Level System Scan Design (LSD) System," to Edward B. Eichelberger, et al. and assigned to the common assignee.
Prior art approaches to designing register files on the same integrated circuit chip with the balance of the combinatorial logic in a microprocessor, for example, employ random access memory (RAM) technology. Typically, a small RAM array will be embodied on the same integrated circuit chip with the balance of the microprocessor circuitry. Typical RAM circuitry has an array of storage cells arranged in rows and columns, each column of storage cells being connected to a pair of bit lines. The bit lines in the RAM configuration are used for both writing data into the respective storage cells and reading data out of the respective storage cells. The clocking arrangement for the RAM configuration is a single clock. Complex logic functions which are embodied in level sensitive scan design (LSSD) technology, require two non-overlapping clocks. Therefore, when a RAM file is embodied on a complex logic function circuit chip employing LSSD technology, the RAM clock must be selected from either the master clock or the slave clock used in the LSSD logic on the balance of the chip. The master clock signal cannot be chosen because the outputs from the RAM file must feed into master latches which would create a race condition violating LSSD design rules. Thus, the slave clock pulse must be chosen as the clock pulse for a RAM file on an integrated circuit chip using LSSD technology. Logic designers can place an artificial delay, for example, in a master clock pulse to delay it sufficiently to enable its use as the RAM clock pulse or alternately logic designers can make use of the slave clock pulse as the RAM clock pulse, but the logic designer does not have the ability to produce more than one clock pulse during a logic cycle for the purpose of clocking the RAM file. Thus the RAM file can either be written into during a logic cycle or read from during a logic cycle, but it cannot be both written into and read from during the same logic cycle.
Since such great dependence is placed upon fast accessing for reading a first address register and writing a second address register in a RAM file for high speed arithmetic and logical operations in microprocessor applications, for example, it is imperative that a register file be capable of both being written into and being read from at differently addressed registers during the same logic cycle for the complex logical function embodied on the same integrated circuit chip. This has not been satisfactorily available in the prior art.